1. Field of Invention
The present invention relates to a method for forming a shallow trench isolation (STI) structure in the semiconductor device process. More particularly, the present invention relates to a method for forming an STI structure with reduced stress.
2. Description of Related Art
In the field of the semiconductor technologies, many semiconductor devices are often integrated and manufactured on identical semiconductor wafer. Therefore, an appropriate isolation structure is necessary between all semiconductor devices on the semiconductor wafer for preventing an undesired electronic leakage or short, which results in a bad semiconductor.
One of the conventional methods for forming the isolation structure is Local Oxidation of Silicon (LOCOS). The fundamental of LOCOS is utilizing a mask to cover a semiconductor device at first, in which only some silicon substrate regions of the semiconductor device where the isolation structures are to be formed in are exposed, and then a thermal oxide (SiO2) layer is grown on the exposed silicon substrate regions by thermal oxidation. The grown SiO2 layers can directly be the isolation structures between the semiconductor devices due to the perfect electrical isolation capability of SiO2.
Both the process and equipment used to form an isolation structure by LOCOS are uncomplicated, but the disadvantages of LOCOS are greater and more apparent in the advanced semiconductor process. For an example, a longer heating time is needed by LOCOS and it involves a higher thermal budgets. Additionally, in the advanced semiconductor process, the feature size of a semiconductor and the distances between devices are smaller and smaller, and the size of a SiO2 isolation structure is also harder and harder to control. Thus, the SiO2 isolation structure will easily extend into the active region of the semiconductor device and cause faults in the semiconductor device.
Therefore, the shallow trench isolation (STI) technique is often utilized to form an isolation structure at present. The fundamental of STI technique is forming the trenches by etching a silicon substrate, and the SiO2 is directly deposited into the trenches in place of the step of forming the SiO2 layer by thermal oxidizing the silicon substrate. Because the size of the trench is very similar to the size of the isolation structure, the size of isolation structure will almost never exceed an expected size, and the problem of the thermal budget with excessive heat is also solved because the heating step is omitted.
FIG. 1 shows a trench structure in an STI structure without the SiO2 layer. It can be seen that a silicon substrate 102 is covered by a pad oxide 104 formed by SiO2, and the pad oxide 104 is covered by a mask layer 106 formed by silicon nitride (Si3N4). The mask layer 106 is used as an etching mask for forming a trench 108 on the silicon substrate 102. Then, a SiO2 layer is grown on the surface of the trench 108 by oxidation in a typical STI process with a high temperature, that is, a liner oxide 110.
In general, the material of a semiconductor wafer substrate is the silicon with single crystal orientation, such as the silicon substrate 102 shown in FIG. 1. Therefore, the oxidation rate is limited by the crystal orientation; that is to say, portions of the silicon substrate with different orientations have different oxidation rates during the thermal oxidation process. According to the foregoing description, when the trench structure shown in FIG. 1 is thermally oxidized, each of the surfaces of the trench 108, such as the lateral and the bottom surfaces, will have different oxidation rates; thus, the SiO2 layer grows with different thicknesses on each corner 112. Therefore, high stress is readily generated in the corner 112, and then a leakage risk appears in the semiconductor devices cause by the high stress in the corner 102 of the trench structure.
According to the foregoing description, when a STI process within a semiconductor process is performed, a method for reducing or eliminating the stress is really needed to reduce or prevent the leakage risk between the semiconductor devices.